The present invention relates generally to semiconductor devices and more particularly to a method and system for providing a contact hole in a semiconductor device structure.
In a conventional semiconductor process, contact holes are used extensively for providing connection between the structures on a semiconductor device. In a conventional process, an etch stop layer is provided on the semiconductor structure to allow for the contact hole to be provided after the other processing steps. This etch stop layer is utilized to create a differential between when etching the device, for example, a gate area, to provide a contact hole.
In conventional semiconductor processing, it is possible that there can be gouging created by the etch even with the etch stop layer due to misalignment issues when providing the contact etch. These misalignment issues could cause gouging into the gate area by the etch, thereby causing a short to the gate area. Accordingly, typically to minimize any possibility of a short from the source/drain (S/D) to the gate problem the distance between the area for providing the contact hole and gate is made very wide to ensure that there is no shorting that would occur. However, as device sizes become smaller and smaller, it becomes more and more difficult and will eventually become impossible to maximize the distance between the contact hole and the gate due to lithographic printing misalignment
Accordingly, what is needed is a system and method for providing a contact hole which minimizes this problem, and at the same time it can provide a wider process margin, prevent the adjacent gate from being exposed, and eliminate a possible short from S/D to gate. The system should be easy to implement, cost effective, and it should be compatible with existing processes. The present invention addresses such a need.
A method and system for providing a contact hole between structures for a semiconductor device is disclosed. The method and system comprises etching a resist material on the semiconductor device to expose a surface of the structures; providing an implant to the surface of the structures; and removing the resist material from a gap between the structures. The method and system includes annealing the semiconductor device to cause the implant to adhere to the treated surface; and providing dielectric material within the gap. Finally, the method and system includes etching the contact hole in the gap between the structures. The contact hole can then be etched without damaging the structures.
Accordingly, by providing an implant treated surface and then providing an anneal process the implant is bonded to the appropriate portion of the semiconductor structure. Due to the etch difference between the implant treated material surface and the non-treated surface, it is possible to etch down to the bottom of the semiconductor device without exposing the gate. Since the surface around the gate structure is treated, the etch stop layer etching at a much slower rate than the structures during the dielectric etching step. Therefore, there is a much larger process margin for misalignment allowance and the contact size can be larger because the dielectric material and the surface treatment protects the gate area.